Extending the functionality of the Internet network layer is notoriously hard. One reason is that, in current networking equipment, extensibility and high performance are often competing goals — if not mutually exclusive. On the one hand, high-end routers, because they rely on specialized and closed hardware and software, are notoriously difficult to extend, program, or otherwise experiment with. On the other hand, “software routers” perform packet-processing in software running on general-purpose platforms; these are easily programmable, but have so far been suitable only for low-packet-rate environments.
Papers etc
Software Dataplane Verification, Mihai Dobrescu and Katerina Argyraki. In NSDI 2014. This paper proposes a set of rules on how to write packet-processing software such that we can formally reason about it. It then presents a verification tool that leverages these rules to prove useful properties (crash-freedom, bounded execution, and reachability properties) about stateless and simple stateful packet-processing pipelines. Our tool proves such properties for Click pipelines within minutes or tens of minutes, whereas a state-of-the-art generic verifier failed to do so within several hours.
Toward a Verifiable Software Dataplane, Mihai Dobrescu and Katerina Argyraki. In HotNets 2013. First ideas on how to write packet-processing software such that we can formally reason about it, e.g., prove that it does not crash independently from workload.
Toward Predictable Performance in Software Packet-Processing Platforms, Mihai Dobrescu, Katerina Argyraki, and Sylvia Ratnasamy. In NSDI 2012. This paper shows that it is feasible to build a software packet-processing system that combines extensibility with predictable, high performance, while supporting a diverse set of packet-processing applications. It presents a simple, Click-based system where (a) different packet-processing tasks affect each other in a predictable manner and (b) the overall performance depends little on how different packet-processing tasks are scheduled on different cores.
Controlling Parallelism in Multi-core Software Routers, Mihai Dobrescu, Katerina Argyraki, Maziar Manesh, Gianluca Iannaccone, and Sylvia Ratnasamy. In the PRESTO 2010 workshop.
Evaluating the Suitability of Server Network Cards for Software Routers, Maziar Manesh, Katerina Argyraki, Mihai Dobrescu, Norbert Egi, Kevin Fall, Gianluca Iannaccone, and Sylvia Ratnasamy. In the PRESTO 2010 workshop.
RouteBricks: Exploiting Parallelism to Scale Software Routers [audio] [video], Mihai Dobrescu and Norbert Egi, Katerina Argyraki, Byung-Gon Chun, Kevin Fall, Gianluca Iannaccone, Allan Knies, Maziar Manesh, and Sylvia Ratnasamy. In SOSP 2009. This paper shows that it is feasible to build a software packet-processing system that performs IP forwarding at multi-Gbps line rates. It presents the design and implementation of the RouteBricks software-router architecture, which parallelizes packet-processing functionality both across multiple servers and across multiple processing cores within a single server. RB4, a RouteBricks prototype consisting of 4 commodity servers, routes up to 24 million packets/sec or 35 Gbps — entirely in software.
Can Software Routers Scale?, Katerina Argyraki, Salman Baset, Byung-Gon Chun, Kevin Fall, Gianluca Iannaccone, Allan Knies, Eddie Kohler, Maziar Manesh, Sergiu Nedevschi, and Sylvia Ratnasamy. In the PRESTO 2008 workshop. This paper introduces the idea of a parallel software-router architecture that consists entirely of off-the-shelf PCs.